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Physical Design & STA

BITSILICA offers complete physical design expertise for Block level and SoC level, from netlist to GDS including Floor Planning, Placement, Clock Tree Synthesis, Routing and Optimization, Timing closure, Signoff Checks like PV, LEC, and STA. We have extensive expertise in different technology nodes(28nm,16nm,10nm,7nm,5nm,4nm).


Our PNR expertise in IO Timing, Floorplanning, PG Planning, Place & Route, Clock Tree Synthesis & Post Route Optimization, is unmatched. We have strong expertise in implementing Low Power techniques related to  Clock Gating, Power Gating, Multi-Vt, Voltage Islands, etc. 
Our team has expertise in using technologies developed by Synopsys (ICC 2 compiler, Primetime, Design compiler) and Cadence (Innovous, Tempus, Genus). 

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